VLSI Design - Indiana University

Thumbnail for VLSI Design Lecture 10.1: Interconnect Part 1

VLSI Design Lecture 10.1: Interconnect Part 1 1 of 46

duration 30 minutes 3 seconds

VLSI Design Lecture 10.1: Interconnect Part 1

Zoom Recording ID: 3910293939 UUID: 2lgQBJYBTiW/NlsGRXypdw== Meeting Time: 2025-04-10 03:18:58amGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 10.2: Interconnect Part 2

VLSI Design Lecture 10.2: Interconnect Part 2 2 of 46

duration 17 minutes 52 seconds

VLSI Design Lecture 10.2: Interconnect Part 2

Zoom Recording ID: 3910293939 UUID: RDKKsH8PTrCtLkZoVdEGXA== Meeting Time: 2025-04-10 03:59:10amGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 10: Logical Effort Part 3

VLSI Design Lecture 10: Logical Effort Part 3 3 of 46

duration 58 minutes 6 seconds

VLSI Design Lecture 10: Logical Effort Part 3

Zoom Recording ID: 88333531208 UUID: fDgH/oJeQROqkqZRM50LwQ== Meeting Time: 2026-02-19 05:49:56pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 11: Layout Tutorial - Multi-fingered transistors

VLSI Design Lecture 11: Layout Tutorial -… 4 of 46

duration 1 hour 0 minutes

VLSI Design Lecture 11: Layout Tutorial -…

VLSI Design Lecture 11: Layout Tutorial - Multi-fingered transistors

VLSI Design Lecture 11: Layout Tutorial -…

VLSI Design Lecture 11: Layout Tutorial - Multi-fingered…

Zoom Recording ID: 88333531208 UUID: EYKd8LNhSGKCPKbzx/j8vw== Meeting Time: 2026-02-24 05:51:19pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 11: SRAM

VLSI Design Lecture 11: SRAM 5 of 46

duration 36 minutes 38 seconds

VLSI Design Lecture 11: SRAM

Zoom Recording ID: 3910293939 UUID: FRHpBk4JTFiS1ZCu0/Y0QA== Meeting Time: 2025-04-10 04:21:29amGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 12.1: Clocking Part 1

VLSI Design Lecture 12.1: Clocking Part 1 6 of 46

duration 12 minutes 56 seconds

VLSI Design Lecture 12.1: Clocking Part 1

Zoom Recording ID: 3910293939 UUID: vkEK/uzjTN6yoChiZ2PDpw== Meeting Time: 2025-04-24 01:42:50pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 12.2: Clocking Part 2

VLSI Design Lecture 12.2: Clocking Part 2 7 of 46

duration 19 minutes 12 seconds

VLSI Design Lecture 12.2: Clocking Part 2

Zoom Recording ID: 3910293939 UUID: SVRwPr2TQsK2PMc7wAjuug== Meeting Time: 2025-04-24 03:44:05pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 12: Complex Logic

VLSI Design Lecture 12: Complex Logic 8 of 46

duration 1 hour 3 minutes

VLSI Design Lecture 12: Complex Logic

Zoom Recording ID: 88333531208 UUID: joyZ6oHHRs6eR2Z7ApHiSg== Meeting Time: 2026-02-26 05:51:20pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 13: Intro to Lab 2 - the XOR Gate

VLSI Design Lecture 13: Intro to Lab 2 - the XOR… 9 of 46

duration 1 hour 5 minutes

VLSI Design Lecture 13: Intro to Lab 2 - the XOR…

VLSI Design Lecture 13: Intro to Lab 2 - the XOR Gate

VLSI Design Lecture 13: Intro to Lab 2 - the XOR…

VLSI Design Lecture 13: Intro to Lab 2 - the XOR Gate

Zoom Recording ID: 88333531208 UUID: 9CRCh68wSc60uJRR5m7CPA== Meeting Time: 2026-03-05 05:50:21pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 14: Layout Design Review / Intro to Final Projects

VLSI Design Lecture 14: Layout Design Review /… 10 of 46

duration 57 minutes 57 seconds

VLSI Design Lecture 14: Layout Design Review /…

VLSI Design Lecture 14: Layout Design Review / Intro to Final Projects

VLSI Design Lecture 14: Layout Design Review /…

VLSI Design Lecture 14: Layout Design Review / Intro to…

Zoom Recording ID: 88333531208 UUID: zmio6DDiSiyZe+kVKXJiiQ== Meeting Time: 2026-03-24 04:40:55pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 15: Power Part 1

VLSI Design Lecture 15: Power Part 1 11 of 46

duration 55 minutes 37 seconds

VLSI Design Lecture 15: Power Part 1

Zoom Recording ID: 88333531208 UUID: jXHs8ktyQHyoHoaO1fNabg== Meeting Time: 2026-03-26 04:57:09pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 16: Power Part 2

VLSI Design Lecture 16: Power Part 2 12 of 46

duration 1 hour 6 minutes

VLSI Design Lecture 16: Power Part 2

Zoom Recording ID: 88333531208 UUID: gaog0YtjRi2Kh8O9P9rcpQ== Meeting Time: 2026-03-31 04:47:42pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 1: Introduction to VLSI Design

VLSI Design Lecture 1: Introduction to VLSI… 13 of 46

duration 1 hour 16 minutes

VLSI Design Lecture 1: Introduction to VLSI…

VLSI Design Lecture 1: Introduction to VLSI Design

VLSI Design Lecture 1: Introduction to VLSI…

VLSI Design Lecture 1: Introduction to VLSI Design

Zoom Recording ID: 88299577927 UUID: UZ+kPU/dRbqzX69MxAKIwA== Meeting Time: 2025-01-14 05:43:37pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 2 - Introduction Part 2

VLSI Design Lecture 2 - Introduction Part 2 14 of 46

duration 1 hour 3 minutes

VLSI Design Lecture 2 - Introduction Part 2

1.0: Slides 14-24

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 2.0: Circuits and Layout Part 1

VLSI Design Lecture 2.0: Circuits and Layout Part… 15 of 46

duration 1 hour 17 minutes

VLSI Design Lecture 2.0: Circuits and Layout Part…

VLSI Design Lecture 2.0: Circuits and Layout Part 1

VLSI Design Lecture 2.0: Circuits and Layout Part…

VLSI Design Lecture 2.0: Circuits and Layout Part 1

Zoom Recording ID: 88299577927 UUID: zT6FaeDRRCWC6kXIIlL5qQ== Meeting Time: 2025-01-16 05:44:19pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 2.1: Circuits and Layout Part 2

VLSI Design Lecture 2.1: Circuits and Layout Part… 16 of 46

duration 23 minutes 8 seconds

VLSI Design Lecture 2.1: Circuits and Layout Part…

VLSI Design Lecture 2.1: Circuits and Layout Part 2

VLSI Design Lecture 2.1: Circuits and Layout Part…

VLSI Design Lecture 2.1: Circuits and Layout Part 2

Zoom Recording ID: 3910293939 UUID: m2Ihx+PMSgyephhoBdmiuw== Meeting Time: 2025-01-20 11:33:26pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 28: Overview of the Preliminary Design Review (PDR)

VLSI Design Lecture 28: Overview of the… 17 of 46

duration 22 minutes 5 seconds

VLSI Design Lecture 28: Overview of the…

VLSI Design Lecture 28: Overview of the Preliminary Design Review (PDR)

VLSI Design Lecture 28: Overview of the…

VLSI Design Lecture 28: Overview of the Preliminary Design…

Zoom Recording ID: 88299577927 UUID: EMGBNvA+Su6h3kpsLH3kHA== Meeting Time: 2025-04-17 04:41:45pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 29: Example Critical Design Review (CDR)

VLSI Design Lecture 29: Example Critical Design… 18 of 46

duration 38 minutes 46 seconds

VLSI Design Lecture 29: Example Critical Design…

VLSI Design Lecture 29: Example Critical Design Review (CDR)

VLSI Design Lecture 29: Example Critical Design…

VLSI Design Lecture 29: Example Critical Design Review (CDR)

Zoom Recording ID: 88299577927 UUID: M5KuqSb7TAergX8Wv4GgDA== Meeting Time: 2025-04-22 04:42:40pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 3 - Introduction Part 3

VLSI Design Lecture 3 - Introduction Part 3 19 of 46

duration 1 hour 1 minute

VLSI Design Lecture 3 - Introduction Part 3

Zoom Recording ID: 3910293939 UUID: fIMnWB0WQAakD4h+v/wGjA== Meeting Time: 2026-01-20 05:49:31pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 3.0: Transistor Theory

VLSI Design Lecture 3.0: Transistor Theory 20 of 46

duration 46 minutes 12 seconds

VLSI Design Lecture 3.0: Transistor Theory

Zoom Recording ID: 88299577927 UUID: IR8h+Rh6Q7ezAE5yDfegvA== Meeting Time: 2025-01-28 05:43:08pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 4 - Introduction to the Cadence EDA

VLSI Design Lecture 4 - Introduction to the… 21 of 46

duration 1 hour 10 minutes

VLSI Design Lecture 4 - Introduction to the…

VLSI Design Lecture 4 - Introduction to the Cadence EDA

VLSI Design Lecture 4 - Introduction to the…

VLSI Design Lecture 4 - Introduction to the Cadence EDA

Zoom Recording ID: 88333531208 UUID: 3qk4WOSaTM+WFW+1ODVLCA== Meeting Time: 2026-01-22 05:45:37pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 4.0: Non-Ideal Transistor Theory Part 1

VLSI Design Lecture 4.0: Non-Ideal Transistor… 22 of 46

duration 1 hour 8 minutes

VLSI Design Lecture 4.0: Non-Ideal Transistor…

VLSI Design Lecture 4.0: Non-Ideal Transistor Theory Part 1

VLSI Design Lecture 4.0: Non-Ideal Transistor…

VLSI Design Lecture 4.0: Non-Ideal Transistor Theory Part 1

Zoom Recording ID: 88299577927 UUID: cFgw5R0vSH2z+JyBmZaodw== Meeting Time: 2025-02-04 05:49:20pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 4.1: Non-Ideal Transistor Theory Part 2 & 5.1: DC & Transient Analysis Part 1

VLSI Design Lecture 4.1: Non-Ideal Transistor… 23 of 46

duration 1 hour 12 minutes

VLSI Design Lecture 4.1: Non-Ideal Transistor…

VLSI Design Lecture 4.1: Non-Ideal Transistor Theory Part 2 & 5.1: DC & Transient Analysis Part 1

VLSI Design Lecture 4.1: Non-Ideal Transistor…

VLSI Design Lecture 4.1: Non-Ideal Transistor Theory Part 2…

Zoom Recording ID: 88299577927 UUID: hgblg4FWSaaGrRnfFQAGjw== Meeting Time: 2025-02-11 05:44:32pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 5 - DC and Transient (Spectre) Simulation in the Cadence EDA

VLSI Design Lecture 5 - DC and Transient… 24 of 46

duration 1 hour 13 minutes

VLSI Design Lecture 5 - DC and Transient…

VLSI Design Lecture 5 - DC and Transient (Spectre) Simulation in the Cadence EDA

VLSI Design Lecture 5 - DC and Transient…

VLSI Design Lecture 5 - DC and Transient (Spectre)…

Zoom Recording ID: 88333531208 UUID: ZGicCBhaRNKRcDs+9EEtbA== Meeting Time: 2026-01-27 05:14:46pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 5.1: DC & Transient Analysis Part 2

VLSI Design Lecture 5.1: DC & Transient… 25 of 46

duration 24 minutes 36 seconds

VLSI Design Lecture 5.1: DC & Transient…

VLSI Design Lecture 5.1: DC & Transient Analysis Part 2

VLSI Design Lecture 5.1: DC & Transient…

VLSI Design Lecture 5.1: DC & Transient Analysis Part 2

Zoom Recording ID: 3910293939 UUID: Q1remxxVQNmZSZusuvQEpw== Meeting Time: 2025-02-13 03:47:50pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 6 - Introduction to Virtuoso Layout Editor

VLSI Design Lecture 6 - Introduction to Virtuoso… 26 of 46

duration 54 minutes 11 seconds

VLSI Design Lecture 6 - Introduction to Virtuoso…

VLSI Design Lecture 6 - Introduction to Virtuoso Layout Editor

VLSI Design Lecture 6 - Introduction to Virtuoso…

VLSI Design Lecture 6 - Introduction to Virtuoso Layout…

Zoom Recording ID: 88333531208 UUID: 1q7OxRaxQL+fy8xdLngOAQ== Meeting Time: 2026-01-29 05:46:11pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 6.1: Logical Effort Part 1

VLSI Design Lecture 6.1: Logical Effort Part 1 27 of 46

duration 24 minutes 14 seconds

VLSI Design Lecture 6.1: Logical Effort Part 1

Zoom Recording ID: 3910293939 UUID: mC4qa2p9QeWA+SB37A+hxg== Meeting Time: 2025-02-20 03:00:25pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 6.2: Logical Effort Part 2

VLSI Design Lecture 6.2: Logical Effort Part 2 28 of 46

duration 15 minutes 12 seconds

VLSI Design Lecture 6.2: Logical Effort Part 2

Zoom Recording ID: 3910293939 UUID: 0iC6UI5NT0amCupyhCFbyw== Meeting Time: 2025-02-20 04:33:20pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 6.3: Logical Effort Part 3

VLSI Design Lecture 6.3: Logical Effort Part 3 29 of 46

duration 19 minutes 42 seconds

VLSI Design Lecture 6.3: Logical Effort Part 3

Zoom Recording ID: 3910293939 UUID: 1EcDRYfsQZ2lAu3Ba65KfA== Meeting Time: 2025-02-20 04:50:17pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 7.1: Power Part 1

VLSI Design Lecture 7.1: Power Part 1 30 of 46

duration 1 hour 9 minutes

VLSI Design Lecture 7.1: Power Part 1

Zoom Recording ID: 88299577927 UUID: 443hqWSXQfCK82yn9Aquig== Meeting Time: 2025-03-06 05:43:30pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 7.2: Power Part 2 + Example IC Design

VLSI Design Lecture 7.2: Power Part 2 + Example… 31 of 46

duration 43 minutes 38 seconds

VLSI Design Lecture 7.2: Power Part 2 + Example…

VLSI Design Lecture 7.2: Power Part 2 + Example IC Design

VLSI Design Lecture 7.2: Power Part 2 + Example…

VLSI Design Lecture 7.2: Power Part 2 + Example IC Design

Zoom Recording ID: 88299577927 UUID: Uh7xejYTSZGADtDW5MRNYQ== Meeting Time: 2025-03-25 04:45:25pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 7: Highlight Reel (3.0 - 5.0) + Pegasus DRC/LVS

VLSI Design Lecture 7: Highlight Reel (3.0 - 5.0)… 32 of 46

duration 1 hour 9 minutes

VLSI Design Lecture 7: Highlight Reel (3.0 - 5.0)…

VLSI Design Lecture 7: Highlight Reel (3.0 - 5.0) + Pegasus DRC/LVS

VLSI Design Lecture 7: Highlight Reel (3.0 - 5.0)…

VLSI Design Lecture 7: Highlight Reel (3.0 - 5.0) + Pegasus…

Zoom Recording ID: 88333531208 UUID: UP0iUeX/Rt2hBmgOb3J5VA== Meeting Time: 2026-02-05 05:45:25pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 8.1: Scaling Part 1

VLSI Design Lecture 8.1: Scaling Part 1 33 of 46

duration 1 hour 5 minutes

VLSI Design Lecture 8.1: Scaling Part 1

Zoom Recording ID: 88299577927 UUID: pNueahEHSvujQMiS+B+3RA== Meeting Time: 2025-03-27 04:38:11pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 8.2: Scaling Part 2

VLSI Design Lecture 8.2: Scaling Part 2 34 of 46

duration 1 hour 8 minutes

VLSI Design Lecture 8.2: Scaling Part 2

Zoom Recording ID: 88299577927 UUID: i2Sx0s6AS7Wk/Fxci6RYcw== Meeting Time: 2025-04-01 04:44:34pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 8: Logical Effort Part 1

VLSI Design Lecture 8: Logical Effort Part 1 35 of 46

duration 1 hour 2 minutes

VLSI Design Lecture 8: Logical Effort Part 1

Zoom Recording ID: 88333531208 UUID: jGuTeNtNQ2aApcoxuhVhKA== Meeting Time: 2026-02-12 05:53:53pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 9: Logical Effort Part 2

VLSI Design Lecture 9: Logical Effort Part 2 36 of 46

duration 1 hour 6 minutes

VLSI Design Lecture 9: Logical Effort Part 2

Zoom Recording ID: 88333531208 UUID: GBWMtb1xSIiYqPxKpJGrqg== Meeting Time: 2026-02-17 05:44:59pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Lecture 9: Sequential Design

VLSI Design Lecture 9: Sequential Design 37 of 46

duration 1 hour 5 minutes

VLSI Design Lecture 9: Sequential Design

Zoom Recording ID: 88299577927 UUID: TXjYX1yaSPyA2RsCCLfwsQ== Meeting Time: 2025-04-03 04:44:28pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Midterm Review

VLSI Design Midterm Review 38 of 46

duration 1 hour 14 minutes

VLSI Design Midterm Review

Zoom Recording ID: 88299577927 UUID: 1MKQGLt/QpuhKhSsUSfhUg== Meeting Time: 2025-03-11 04:43:02pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Tutorial: DRC & LVS

VLSI Design Tutorial: DRC & LVS 39 of 46

duration 56 minutes 31 seconds

VLSI Design Tutorial: DRC & LVS

Zoom Recording ID: 88299577927 UUID: UkEMJ4KJS7Ss65+N7rzQTQ== Meeting Time: 2025-02-06 05:46:52pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Tutorial: Intro to HW 2

VLSI Design Tutorial: Intro to HW 2 40 of 46

duration 50 minutes 54 seconds

VLSI Design Tutorial: Intro to HW 2

Zoom Recording ID: 88299577927 UUID: xVKjoGkxR9mZ67uUE/VYqA== Meeting Time: 2025-03-04 05:41:03pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Tutorial: IU Standard Cell Library

VLSI Design Tutorial: IU Standard Cell Library 41 of 46

duration 15 minutes 57 seconds

VLSI Design Tutorial: IU Standard Cell Library

Zoom Recording ID: 88299577927 UUID: o1HUH5B0SWSE6w0pBKwtFA== Meeting Time: 2025-02-20 05:40:09pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Tutorial: Layout of a NAND2

VLSI Design Tutorial: Layout of a NAND2 42 of 46

duration 1 hour 18 minutes

VLSI Design Tutorial: Layout of a NAND2

Zoom Recording ID: 88299577927 UUID: y4xU73z3SJ+qWCa9gbNjhA== Meeting Time: 2025-01-23 05:43:47pmGMT

From Daniel Loveless

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Thumbnail for VLSI Design Tutorial: Vias

VLSI Design Tutorial: Vias 43 of 46

duration 15 minutes 41 seconds

VLSI Design Tutorial: Vias

Zoom Recording ID: 88299577927 UUID: bd8cS3qvS1u6nue/S/wYSQ== Meeting Time: 2025-01-30 05:45:26pmGMT

From Daniel Loveless

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VLSI Design: Lab 1 Intro 44 of 46

duration 12 minutes 6 seconds

VLSI Design: Lab 1 Intro

Zoom Recording ID: 88299577927 UUID: kXHFyHJ8RymgGUE0PQoxwg== Meeting Time: 2025-01-21 05:41:44pmGMT

From Daniel Loveless

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VLSI Design: Lab 2 Intro 45 of 46

duration 1 hour 0 minutes

VLSI Design: Lab 2 Intro

Zoom Recording ID: 88299577927 UUID: qpQ61lmJSGOXkHiVcyuobw== Meeting Time: 2025-02-13 05:44:39pmGMT

From Daniel Loveless

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VLSI Design: Lab 2 Q&A 46 of 46

duration 41 minutes 47 seconds

VLSI Design: Lab 2 Q&A

Zoom Recording ID: 88299577927 UUID: UBP+zVUITWu4s94k77vaoA== Meeting Time: 2025-02-27 05:41:15pmGMT

From Daniel Loveless

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